Module arch 

Re-exports

pub use x86_64::packed_aes_256;

pub use x86_64::packed_aes_512;

pub use x86_64::packed_ghash_256;

pub use x86_64::packed_ghash_512;

pub use x86_64::M256;

pub use x86_64::M512;

pub use x86_64::m256_from_u128s;

pub use x86_64::packed_ghash_256::GhashWideMul2x;

pub use x86_64::packed_ghash_256::GhashSquare2x;

pub use x86_64::packed_ghash_256::GhashInvert2x;

pub use x86_64::packed_ghash_512::GhashWideMul4x;

pub use x86_64::packed_ghash_512::GhashSquare4x;

pub use x86_64::packed_ghash_512::GhashInvert4x;

pub use x86_64::packed_aes_256::AesWideMul32x;

pub use x86_64::packed_aes_256::AesSquare32x;

pub use x86_64::packed_aes_256::AesInvert32x;

pub use x86_64::packed_aes_512::AesWideMul64x;

pub use x86_64::packed_aes_512::AesSquare64x;

pub use x86_64::packed_aes_512::AesInvert64x;

pub use portable::arithmetic::itoh_tsujii::invert_b128;

pub use portable::packed_aes_8;

pub use portable::packed_aes_8::AesInvert1x;

pub use portable::packed_aes_8::AesSquare1x;

pub use portable::packed_aes_8::AesWideMul1x;

Modules

packed_aes_128

packed_ghash_128

PCLMULQDQ-accelerated implementation of GHASH for x86_64.

portable

Structs

BytewiseLookup

Square and invert strategy for the 1×8b AES packing: a direct table lookup on the underlying byte. Wider AES packings reach this one byte at a time through the Divide strategy, so no AES arithmetic is ever defined in terms of (packed) scalar iteration.

Divide

Strategy that splits the underlier into SubU-sized lanes, applies the sub-packing PackedPrimitiveType<SubU, F>’s op to each lane, and recombines — a generic fallback for packings that lack a specialized full-width Square, InvertOrZero, or WideMul. The sub-underlier SubU is a PhantomData parameter so the packing type T stays last for the macro’s Divide<SubU, $name, N> form.

LaneWideProduct

One independent deferred wide product per SubU lane of a Divide widening multiply. Lanes accumulate (Add/Sub/Sum) and reduce independently, mirroring the packing structure, so a sum of products is reduced only once per lane. N is the lane count.

M128

128-bit value that is used for 128-bit SIMD operations

MulFromWideMul

Wrapper that defines multiplication as reduce(wide_mul(a, b)), deferring to the type’s own WideMul impl, making the widening multiply the single source of truth for both Mul and WideMul. Used by every GHASH and AES packing.

PackedPrimitiveType

PairwiseStrategy

Pairwise strategy. Apply the result of the operation to each packed element independently.

ReuseMultiply

Square wrapper that reuses the type’s own multiplication: square(x) = x * x.

Scaled

Wrapper for ScaledUnderlier multiplication that delegates to sub-underlier operations.

Type Aliases

AesInvert16x

AesSquare16x

AesWideMul16x

GhashInvert1x

Invert wrapper for the PackedBinaryGhash1x128b packing: the shared Itoh-Tsujii inversion (there is no CLMUL inverse).

GhashSquare1x

GhashWideMul1x

OptimalB128

OptimalPackedB1

OptimalPackedB128