Expand description
Experimental portable, auto-vectorized Blake3 multi-lane kernel.
Two batched entry points share one block-compression core:
- Leaf hashing, for any message up to one 1024-byte chunk.
- Two-to-one inner-node compression,
blake3(left || right)over a 64-byte pair.
An alternative to driving the blake3 crate’s hand-written SIMD kernel.
The bet: LLVM auto-vectorizes plain lane loops into whatever the target has.
- Each of the 16 compression-state words is held as
[u32; N], one lane per message. - Every step is a fixed-width
0..Nloop of plain scalaru32arithmetic. - No intrinsics, no
unsafe, no per-target code.
Lanes the vectorizer is expected to fill, per target:
- NEON (128-bit) on ARM64 -> 4 lanes per vector.
- AVX2 / AVX-512 on x86 -> 8 / 16 lanes per vector.
- SVE2 on capable ARM64 -> width-agnostic vectors.
Output is bit-identical to blake3::hash, pinned to the reference in tests.
Scope: any message up to one 1024-byte chunk, including sub-block and partial-block leaves.
Structs§
- Portable
Blake3 Multi Digest - Portable multi-lane Blake3 leaf digest over
Nmessages, hashed a block at a time. - Portable
Blake3 Parallel Compression - Parallel Blake3 two-to-one compression backed by the portable auto-vectorized kernel.
- Portable
Blake3 Parallel Digest - Parallel Blake3 leaf digest backed by the portable auto-vectorized kernel.