binius_hal/
lib.rs

1// Copyright 2024-2025 Irreducible Inc.
2
3//! The hardware abstraction layer (HAL) provides an interface for expensive computations that can
4//! be run with hardware acceleration.
5//!
6//! The HAL is consumed by the `binius_core` crate. The interfaces are currently designed around
7//! the architecture of [Irreducible's](https://www.irreducible.com) custom FPGA platform. The
8//! crate exposes a default, portable CPU backend that can be created with
9//! [`crate::make_portable_backend`].
10
11mod backend;
12mod common;
13mod cpu;
14mod error;
15mod sumcheck_evaluator;
16mod sumcheck_folding;
17mod sumcheck_multilinear;
18mod sumcheck_round_calculation;
19
20pub use backend::*;
21pub use cpu::*;
22pub use error::*;
23pub use sumcheck_evaluator::*;
24pub use sumcheck_multilinear::*;